1. Field of the Invention
This invention relates generally to signal routing, and, more particularly, to a method and apparatus for signal routing to achieve signal-efficiency and reduce signal skew on circuit boards.
2. Description of the Related Art
The proliferation of the high-technology industry has resulted in many innovations that improve our ability to create useful electronic devices. One commodity that is at a premium in electronics devices is the integrated chip. Integrated chips and other specialized electronic circuitry have become integral parts of electronic devices. Therefore, the need to mass-produce integrated chips and other electronic circuitry has generated the need for creative solutions for certain manufacturing issues. Many of these manufacturing issues are not readily contemplated by many in the field. One such issue arises when a testing phase is implemented during the manufacturing of integrated chips and other electronic circuitry.
During the testing phase of semiconductor chips, and other electronic circuitry, multiple sets of a single product are tested together. Generally, to help achieve efficiency in the manufacturing process, devices are tested in groups. To facilitate testing of an array of products, several signals are generally routed between these products and a centralized system. To effectively test the products being manufactured, several or even substantially all of the functionality of a product are tested. To achieve a thorough test of multiple products in a test group, many signals must interface with these products. These signals include data signals, address signals, read control, write control, enable, and other control signals.
Often, there are a substantial number of devices that are tested within a single group. This generally requires a large number of signals that must be routed to each of the devices being tested. Generally, the routing of multiple test-signals leads to significant signal-path lengths and the need to run multiple signals side by side. This causes signal skew problems.
Signal timing is crucial during testing of semiconductor and electronic devices. Many time-critical tests of semiconductor and electronic devices are conducted, particularly during the manufacturing phase. Furthermore, many of these tests are conducted under burn-in conditions. During bum-in conditions, the devices being tested are often isolated in temperature and pressure chambers. These testing chambers should not be disturbed during the testing process. Thus, the accurate performance of the data, address, and control signals that facilitate communications between the devices being tested and the testing system is very important.
The primary problem with state-of-the-art testing procedures is that signal problems, such as propagation delays and other timing problems, often arise. Many times, semiconductor and electronic devices are arranged in arrays on a test-product carrier. The devices being controlled are generally addressed in a logical manner, such as a row and column scheme of addressing using an (x, y)-coordinate system. For example, if an entire column of devices is to be tested, then a selector signal that addresses that particular column is asserted. Also, all of the signals that address the rows are also asserted. The devices that are in the path of the intersection of the asserted column signal and the asserted row signal are addressed. The problem with this arrangement is that errors may occur during accurate timing analysis of the performance of the devices being tested.
The timing problems occur when the devices residing in the first part of the column are turned on slightly sooner than the devices in the latter part of the column, in relation to the signals that were running row-wise. This occurs because the control signals are running in different x, y directions. The timing problem here is a result of signal propagation delay which results in signal skew problems. State-of-the-art testing equipment lacks a routing methodology that allows both selector signals (row selector and column selector) to run in a single access path, reducing the effects of signal skew. Furthermore, current testing equipment lacks a method of addressing multiple devices that compensates for unavoidable signal propagation delays.
A new method of addressing multiple semiconductor and electronic devices that avoids signal skew problems, even in isolated testing situations, is needed. The efficiency of the large amount of testing that takes place in the high technology industry would dramatically improve due to such an innovation. The testing of devices, particularly in isolated conditions, would become more efficient and less costly. Such advancement would dramatically improve manufacturing processes, in terms of efficiency and accuracy, for many high technology industries. Such an innovative addressing scheme can also be used for other applications, including memory array designs, which may lead to new types of semiconductor and electronic devices.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.